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| SSM2302N N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Capable of 2.5V gate drive Small package outline Surface-mount package S D BV DSS RDS(ON) ID 20V 85m 2.8A Description SOT-23 G Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, low on-resistance and cost-effectiveness. D G S Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current , VGS @ 4.5V Continuous Current , VGS @ 4.5V Pulsed Drain Current 1,2 3 3 Rating 20 12 2.8 2.2 10 1.25 0.01 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 100 Unit C/W Rev.2.02 3/12/2004 www.SiliconStandard.com 1 of 6 SSM2302N Electrical Characteristics @ Tj=25 C (unless otherwise specified) Symbol BVDSS BV DSS/ Tj o Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 20 0.5 - Typ. 0.1 6 4.4 0.6 1.9 5.2 37 15 5.7 145 100 50 Max. Units 85 115 1 10 100 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA RDS(ON) Static Drain-Source On-Resistance VGS=4.5V, ID=3.6A VGS=2.5V, ID=3.1A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=55 C) o o VDS=VGS, ID=250uA VDS=5V, ID=3.6A VDS=20V, VGS=0V VDS=20V ,VGS=0V VGS= 12V ID=3.6A VDS=10V VGS=4.5V VDS=10V ID=3.6A RG=6 ,VGS=5V RD=2.8 VGS=0V VDS=10V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol IS ISM VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=1.2V 1 Min. - Typ. - Max. Units 1.6 10 1.2 A A V Pulsed Source Current ( Body Diode ) Forward On Voltage 2 IS=1.6A, VGS=0V Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t < 5 sec. Rev.2.02 3/12/2004 www.SiliconStandard.com 2 of 6 SSM2302N 10 6 T C =25 o C 8 V G =4.5V V G =3.5V V G =3.0V T C =150 o C V G =4.5V V G =3.5V V G =3.0V ID , Drain Current (A) ID , Drain Current (A) V G =2.5V 6 4 V G =2.5V V G =2.0V 4 2 V G =2.0V 2 0 0 1 2 3 0 0 1 2 3 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 1.8 I D = 3.6 A 90 I D =3.6A 1.6 T C =25 C o V G =4.5V RDSON (m ) 80 Normalized R DS(ON) 2 3 4 5 1.4 1.2 70 1.0 60 0.8 50 0.6 -50 0 50 100 150 V GS (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature Rev.2.02 3/12/2004 www.SiliconStandard.com 3 of 6 SSM2302N 4 2 3 1.5 ID , Drain Current (A) 2 PD (W) 25 50 75 100 125 150 1 1 0.5 0 0 0 50 100 150 T c , Case Temperature ( o C) T c , Case Temperature ( C) o Fig 5. Maximum Drain Current vs. Case Temperature Fig 6. Typical Power Dissipation 100 1 DUTY=0.5 10 Normalized Thermal Response (R thja) 0.2 ID (A) 0.1 1ms 0.1 0.05 PDM 1 t SINGLE PULSE 10ms T Duty factor = t/T Peak Tj = P DM x Rthja + Ta 0.02 T c =25 C Single Pulse 0.1 1 10 o 100ms 1s 0.01 100 0.0001 0.001 0.01 0.1 1 10 100 V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance Rev.2.02 3/12/2004 www.SiliconStandard.com 4 of 6 SSM2302N 12 f=1.0MHz 1000 10 I D =3.6A V DS =4.5V VGS , Gate to Source Voltage (V) 8 6 C (pF) Ciss 100 Coss 4 Crss 2 0 0 1 2 3 4 5 6 7 8 9 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 100.0 1.6 1.4 1.2 10.0 VGS(th) (V) T j =25 o C T j =150 o C 1 IF (A) 0.8 1.0 0.6 0.4 0.1 0.1 0.5 0.9 1.3 0.2 -50 0 50 100 150 V SD (V) T j , Junction Temperature ( C ) o Fig 11. Forward Characteristic of Reverse Diode Fig 12. Gate Threshold Voltage vs. Junction Temperature Rev.2.02 3/12/2004 www.SiliconStandard.com 5 of 6 SSM2302N VDS RD 90% D VDS TO THE OSCILLOSCOPE 0.5x RATED VDS RG G + 5v - S VGS 10% VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE QG 4.5V D G S + 0.5 x RATED VDS QGS QGD VGS 1~ 3 mA IG ID Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.02 3/12/2004 www.SiliconStandard.com 6 of 6 |
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